1. Field of Invention
Example embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same, more particularly, to a three-dimensional floating gate NAND flash memory device and a method of manufacturing the same.
2. Description of Related Art
A semiconductor device may include memory cells that are arranged in two dimensions on a semiconductor substrate. The integration of memory cells has been increased by reducing memory cell size within a predetermined area of a semiconductor substrate in order to achieve a high level of integration of a semiconductor device. However, a reduction in the size of memory cells is reaching physical limits. To overcome these physical limits, a semiconductor device having a three-dimensional structure in which memory cells are arranged in three dimensions has been developed.
A three-dimensional structured semiconductor device can efficiently utilize the area of a semiconductor substrate and improve the degree of integration as compared with a semiconductor device that has memory cells arranged in two dimensions. In particular, there are ongoing attempts to uniformly arrange memory cells in a NAND flash memory device, which is appropriately designed to achieve a high level of integration, in a three-dimensional structure.
According to a method of manufacturing a conventional three-dimensional NAND flash memory device, a stack structure is formed of a plurality of conductive layers and a plurality of interlayer insulating layers are alternately stacked one upon another on a semiconductor substrate, a vertical hole that passes through the stack structure is formed, and a charge trap layer and a channel layer are formed in the vertical hole. The charge trap layer is formed on a sidewall of the vertical hole, while the vertical hole having the charge trap layer therein is filled with the channel layer. The charge trap layer is a SiN layer capable of trapping electric charge. The above-described conventional three-dimensional NAND flash memory device has Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cells formed at intersections between channel layers and conductive layers. A SONOS memory cell has a deteriorated data retention characteristic and a lower erase speed in comparison with a floating-gate memory cell. Therefore, there is a need for a three-dimensional NAND flash memory device that has floating-gate memory cells with improved operating characteristics of a three-dimensional semiconductor device.
FIG. 1 is a cross-sectional view of a conventional floating gate type three-dimensional NAND flash memory device.
With reference to FIG. 1, the floating gate type three-dimensional NAND flash memory device includes a vertical channel layer 121; a tunnel insulating layer 119 formed on a sidewall of the vertical channel layer 121; a plurality of control gates CG stacked one upon another in a direction in which the vertical channel layer 121 extends and separated from each other with interlayer insulating layers 105a, 105b, 105c, 105d, and 105e interposed therebetween; floating gates FG formed between the plurality of control gates CG and covering the vertical channel layer 121 with the tunnel insulating layer 119 interposed therebetween; and a dielectric layer 115 formed between the floating gates FG and the control gates CG.
The plurality of control gates CG are formed by patterning a plurality of first conductive layers 107a, 107b, 107c, and 107d stacked one upon another and separated from each other with the interlayer insulating layers 105a, 105b, 105c, 105d, and 105e interposed therebetween, respectively. The first conductive layers 107a, 107b, 107c, and 107d may be silicon layers.
The dielectric layer 115 is formed along the surface of a vertical hole and the surface of a recessed region that extends from the vertical hole to the plurality of interlayer insulating layers 105a, 105b, 105c, 105d, and 105e. The vertical hole is formed by etching the plurality of first conductive layers 107a, 107b, 107c, and 107d and the plurality of interlayer insulating layers 105a, 105b, 105c, 105d, and 105e. The recessed region is formed by etching the plurality of interlayer insulating layers 105a, 105b, 105c, 105d, and 105e exposed through the vertical hole after the vertical hole is formed. When the recessed region is formed, sidewalls of the plurality of first conductive layers 107a, 107b, 107c, and 107d adjacent to the vertical hole protrude further than those of the plurality of interlayer insulating layers 105a, 105b, 105c, 105d, and 105e. 
The floating gates FG are formed by filling the recessed regions with a second conductive layer 117 after the dielectric layer 115 is formed. The second conductive layer 117 may be a silicon layer.
The tunnel insulating layer 119 is formed on the sidewall of the vertical hole including sidewalls of the floating gates FG after the floating gates FG are formed. The tunnel insulating layer 119 has a thickness that allows electrons to pass by the tunnel effect when voltage having a predetermined level or higher is applied between the vertical channel layer 121 and the floating gates FG.
The vertical channel layer 121 may be formed by filling the vertical hole with a semiconductor material, such as silicon, after the tunnel insulating layer 119 is formed.
Memory cells are formed at intersections between the floating gates FG and the vertical channel layer 121. The memory cells are coupled in series in the direction in which the vertical channel layer 121 extends, thereby forming strings.
The above-described semiconductor device controls the voltage applied to the vertical channel layer 121 and the control gates CG to thereby accumulate charges on the floating gates FG. In order to write data in a selected floating gate FG_1, a program bias having a higher level than the voltage of the vertical channel layer 121 is applied to a pair of control gates CG_1 and CG_2 disposed over and under the selected floating gate FG_1. Electrons are thereby injected into the selected floating gate FG_1 to increase a threshold voltage of a selected memory cell.
During the above-described program operation, the program bias may cause undesirable injection of electrons into unselected floating gate FG_2 and FG_3 adjacent to the pair of control gates CG_1 and CG_2. In this case, a disturbance phenomenon occurs, that is, a threshold voltage of each of the unselected memory cells disposed over and under the selected memory cell changes.
Each of the memory cells of the conventional floating gate type three-dimensional NAND flash memory device is driven by two control gates CG stacked one upon another. Therefore, in order to form the memory cells constituting the strings, two more control gates CG than the number of floating gates FG need to be stacked. Further, because the two control gates used to drive a particular memory cell are shared by another memory cell disposed over or under the particular memory cell, operating conditions for driving the particular memory cell is complicated.